LOW COST REVERSIBLE SIGNED COMPARATOR

Author
Farah Sharmin,
Computer Science and Engineering
University of Dhaka
Rajib Kumar Mitra,
Computer Science and Engineering
Patuakhali Science and Technology University,
Anisur Rahman
Computer Science and Engineering
Daffodil International University
ABSTRACT
Nowadays  exponential  advancement  in  reversible  computation  has  lead  to  better fabrication  and integration  process.  It  has  become  very  popular  over  the  last  few years  since  reversible  logic  circuits dramatically reduce energy loss. It consumes less power by recovering bit loss from its unique input-output mapping.    This  paper  presents two  new  gates  called  RC-I  and  RC-II  to  design  an  n-bit  signed  binary comparator where simulation results show that the proposed circuit works correctly and gives significantly better  performance  than  the  existing  counterparts.  An  algorithm  has  been presented  in  this  paper  for constructing an optimized  reversible n-bit  signed comparator circuit. Moreover  some  lower bounds have been  proposed  on  the  quantum  cost,  the numbers  of  gates  used  and  the  number  of  garbage  outputs generated  for designing a low cost   reversible  signed comparator. The comparative study shows  that  the proposed design exhibits superior performance considering all the efficiency parameters of reversible logic design  which  includes  number  of  gates  used,  quantum  cost,  garbage  output  and constant  inputs.  This proposed design has certainly outperformed all the other existing approaches.
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