Tag Archives: Farah Sharmin

LOW COST REVERSIBLE SIGNED COMPARATOR

Farah Sharmin,
Computer Science and Engineering
University of Dhaka
Rajib Kumar Mitra,
Computer Science and Engineering
Patuakhali Science and Technology University,
Anisur Rahman
Computer Science and Engineering
Daffodil International University
Nowadays  exponential  advancement  in  reversible  computation  has  lead  to  better fabrication  and integration  process.  It  has  become  very  popular  over  the  last  few years  since  reversible  logic  circuits dramatically reduce energy loss. It consumes less power by recovering bit loss from its unique input-output mapping.    This  paper  presents two  new  gates  called  RC-I  and  RC-II  to  design  an  n-bit  signed  binary comparator where simulation results show that the proposed circuit works correctly and gives significantly better  performance  than  the  existing  counterparts.  An  algorithm  has  been presented  in  this  paper  for constructing an optimized  reversible n-bit  signed comparator circuit. Moreover  some  lower bounds have been  proposed  on  the  quantum  cost,  the numbers  of  gates  used  and  the  number  of  garbage  outputs generated  for designing a low cost   reversible  signed comparator. The comparative study shows  that  the proposed design exhibits superior performance considering all the efficiency parameters of reversible logic design  which  includes  number  of  gates  used,  quantum  cost,  garbage  output  and constant  inputs.  This proposed design has certainly outperformed all the other existing approaches.
For details please see the attached file:

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Design of a Compact Reversible Random Access Memory

Farah Sharmin,
Computer Science and Engineering
University of Dhaka
Md. Masbaul Alam Polash,
Computer Science and Engineering
University of Dhaka
Md. Shamsujjoha
Computer Science and Engineering
University of Dhaka
viagra dla kobiet Abstract—
Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Thus reversible logic has become immensely popular research area and its applications have spread in various technologies. In this paper we have proposed the reversible logic synthesis of Random Access Memory with a newly proposed 3 × 3 reversible gate named as FS. This reversible design of Random Access Memory has less number of gates, garbage outputs and quantum cost compared with the existing ones. In the way of designing a reversible Random Access Memory we have proposed n × 2n reversible decoder, reversible D flip-flop and write-enabled master-slave D flip-flop which have outperformed those described in the literature. Moreover we have proposed five lower bounds for designing reversible decoder as well as reversible Random Access Memory.
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https://www.apprhs.org/heartbeat/ed/se-puede-comprar-viagra-sin-receta-medica.html

Design and Minimization of Reversible Circuits for a Data Acquisition and Storage System

Lafifa Jamal,
Computer Science and Engineering
Daffodil International University
Farah Sharmin,
Computer Science and Engineering
Daffodil International University
Md. Abdul Mottalib
Computer Science and Information Technology
Islamic University of Technology,

https://www.apprhs.org/heartbeat/ed/viagra-weight-gain.html https://www.apprhs.org/heartbeat/ed/buy-levitra-from-germany.html ABSTRACT

source url Reducing power dissipation is the ultimate objective in the world of VLSI circuit design. Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Thus reversible logic has become immensely popular research area and its applications have spread in various technologies. In this paper we have proposed the compact design of reversible circuits for a data acquisition and storage system. The design comprises with a compact reversible analog-to- digital converter and a reversible address register. In the way of designing this data acquisition and storage system we have proposed a reversible J-K flip-flop with asynchronous inputs, a reversible D flip-flop and a reversible three state buffer register. All the reversible designs individually have less number of gates, garbage outputs and quantum cost compared with the existing ones and have outperformed those described in the literature. Moreover we have proposed some lower bounds for designing these reversible components of the compact data acquisition and storage system.

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LOW COST REVERSIBLE SIGNED COMPARATOR

Rashida Hasan
Daffodil International University
Farah Sharmin
Computer Science and Engineering
University of Dhaka
Rajib Kumar Mitra
Patuakhali Science and Technology University
ABSTRACT:
Nowadays  exponential  advancement  in  reversible computation  has  lead  to  better  fabrication  and integration  process.  It  has  become  very  popular  over  the  last  few  years  since  reversible  logic  circuits dramatically reduce energy loss. It consumes less power by recovering bit loss from its unique input-output mapping.    This  paper  presents  two  new  gates  called  RC-I  and  RC-II  to  design  an  n-bit  signed  binary comparator where simulation results show that the proposed circuit works correctly and gives significantly better  performance  than  the  existing  counterparts.  An  algorithm  has  been presented  in  this  paper  for constructing an optimized  reversible n-bit  signed comparator circuit. Moreover  some  lower bounds have been  proposed  on  the  quantum  cost,  the numbers  of  gates  used  and  the  number  of  garbage  outputs generated  for designing a low cost   reversible  signed comparator. The comparative study shows  that  the proposed design exhibits superior performance considering all the efficiency parameters of reversible logic design  which  includes  number  of  gates  used,  quantum  cost,  garbage  output  and constant  inputs.  This proposed design has certainly outperformed all the other existing approaches.
For details please see the attached file: