Tag Archives: Hafiz Md. Hasan Babu

Design of a Compact Reversible Random Access Memory

Author
Farah Sharmin,
Computer Science and Engineering
University of Dhaka
Md. Masbaul Alam Polash,
Computer Science and Engineering
University of Dhaka
Md. Shamsujjoha
Computer Science and Engineering
University of Dhaka
Abstract—
Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Thus reversible logic has become immensely popular research area and its applications have spread in various technologies. In this paper we have proposed the reversible logic synthesis of Random Access Memory with a newly proposed 3 × 3 reversible gate named as FS. This reversible design of Random Access Memory has less number of gates, garbage outputs and quantum cost compared with the existing ones. In the way of designing a reversible Random Access Memory we have proposed n × 2n reversible decoder, reversible D flip-flop and write-enabled master-slave D flip-flop which have outperformed those described in the literature. Moreover we have proposed five lower bounds for designing reversible decoder as well as reversible Random Access Memory.
For details please see the attached file:

Design and Minimization of Reversible Circuits for a Data Acquisition and Storage System

Author
Lafifa Jamal,
Computer Science and Engineering
Daffodil International University
Farah Sharmin,
Computer Science and Engineering
Daffodil International University
Md. Abdul Mottalib
Computer Science and Information Technology
Islamic University of Technology,

ABSTRACT

Reducing power dissipation is the ultimate objective in the world of VLSI circuit design. Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Thus reversible logic has become immensely popular research area and its applications have spread in various technologies. In this paper we have proposed the compact design of reversible circuits for a data acquisition and storage system. The design comprises with a compact reversible analog-to- digital converter and a reversible address register. In the way of designing this data acquisition and storage system we have proposed a reversible J-K flip-flop with asynchronous inputs, a reversible D flip-flop and a reversible three state buffer register. All the reversible designs individually have less number of gates, garbage outputs and quantum cost compared with the existing ones and have outperformed those described in the literature. Moreover we have proposed some lower bounds for designing these reversible components of the compact data acquisition and storage system.

For details please see the following link: