Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Thus reversible logic has become immensely popular research area and its applications have spread in various technologies. In this paper we have proposed the reversible logic synthesis of Random Access Memory with a newly proposed 3 × 3 reversible gate named as FS. This reversible design of Random Access Memory has less number of gates, garbage outputs and quantum cost compared with the existing ones. In the way of designing a reversible Random Access Memory we have proposed n × 2n reversible decoder, reversible D flip-flop and write-enabled master-slave D flip-flop which have outperformed those described in the literature. Moreover we have proposed five lower bounds for designing reversible decoder as well as reversible Random Access Memory.