Tag Archives: Rashida Hasan

LOW COST REVERSIBLE SIGNED COMPARATOR

Author
Farah Sharmin,
Computer Science and Engineering
University of Dhaka
Rajib Kumar Mitra,
Computer Science and Engineering
Patuakhali Science and Technology University,
Anisur Rahman
Computer Science and Engineering
Daffodil International University
ABSTRACT
Nowadays  exponential  advancement  in  reversible  computation  has  lead  to  better fabrication  and integration  process.  It  has  become  very  popular  over  the  last  few years  since  reversible  logic  circuits dramatically reduce energy loss. It consumes less power by recovering bit loss from its unique input-output mapping.    This  paper  presents two  new  gates  called  RC-I  and  RC-II  to  design  an  n-bit  signed  binary comparator where simulation results show that the proposed circuit works correctly and gives significantly better  performance  than  the  existing  counterparts.  An  algorithm  has  been presented  in  this  paper  for constructing an optimized  reversible n-bit  signed comparator circuit. Moreover  some  lower bounds have been  proposed  on  the  quantum  cost,  the numbers  of  gates  used  and  the  number  of  garbage  outputs generated  for designing a low cost   reversible  signed comparator. The comparative study shows  that  the proposed design exhibits superior performance considering all the efficiency parameters of reversible logic design  which  includes  number  of  gates  used,  quantum  cost,  garbage  output  and constant  inputs.  This proposed design has certainly outperformed all the other existing approaches.
For details please see the attached file:

Self Adaptive Differential Evolution (SaDE) for Handling Economic Load Dispatch with Valve-point Effect, Multiple Fuel & Transmission Losses

Author
Rashida Hasan
Computer Science & Engineering
University of Dhaka
Farhana Haque
Computer Science and Engineering
University of Dhaka
Abstract—This paper presents the solution of economic load dispatch (ELD) problem of generating units with valve-point effects, multiple fuel options and transmission losses using selfadaptive differential evolution (SaDE) algorithm. SaDE has found effective in solving many real world constrained optimization problems in different domains. In this paper, the
key parameters of control in DE algorithm are self-adapted according to their previous experiences of generating promising solution. Five different test cases were applied to prove the effectiveness of the proposed approach. Compared with the other existing techniques, the proposed algorithm has been found to perform better in a number of cases. Considering the quality of the solution obtained, this method seems to be a promising approach for solving economic load dispatch problem. Keywords— Economic load dispatch problem, valve-point effect, multiple fuel, transmission losses, self-adaptive differential evolution.
For details please see the attached file:

Data Mining Techniques for Informative Motif Discovery

Author
Rashida Hasan
Computer Science & Engineering
University of Dhaka
Jainal Uddin
Computer Science and Engineering
University of Dhaka

ABSTRACT:

The discovery of motifs in biological sequence is a much explored and still exploring area of research in functional genomics since they control the expression or regulation of a group of genes involved in a similar cellular function. This paper explores the use of data mining techniques by various researchers as a solution to discover motifs in biological sequence. Although data mining techniques has not been applied extensively by researchers as compared to other algorithms. But in recent years data mining techniques has caused a wide attention by the researchers to find motifs in biological sequence. This paper is an attempt towards exploring the effectiveness of data mining techniques for motif discovery.

For details please see the attached file:

LOW COST REVERSIBLE SIGNED COMPARATOR

Author
Rashida Hasan
Daffodil International University
Farah Sharmin
Computer Science and Engineering
University of Dhaka
Rajib Kumar Mitra
Patuakhali Science and Technology University
ABSTRACT:
Nowadays  exponential  advancement  in  reversible computation  has  lead  to  better  fabrication  and integration  process.  It  has  become  very  popular  over  the  last  few  years  since  reversible  logic  circuits dramatically reduce energy loss. It consumes less power by recovering bit loss from its unique input-output mapping.    This  paper  presents  two  new  gates  called  RC-I  and  RC-II  to  design  an  n-bit  signed  binary comparator where simulation results show that the proposed circuit works correctly and gives significantly better  performance  than  the  existing  counterparts.  An  algorithm  has  been presented  in  this  paper  for constructing an optimized  reversible n-bit  signed comparator circuit. Moreover  some  lower bounds have been  proposed  on  the  quantum  cost,  the numbers  of  gates  used  and  the  number  of  garbage  outputs generated  for designing a low cost   reversible  signed comparator. The comparative study shows  that  the proposed design exhibits superior performance considering all the efficiency parameters of reversible logic design  which  includes  number  of  gates  used,  quantum  cost,  garbage  output  and constant  inputs.  This proposed design has certainly outperformed all the other existing approaches.
For details please see the attached file: