In this study, a digital logic system is designed and implemented using a Xilinx Spartan-6 FPGA board. Using the Xilinx ISE Design Suite 14.7, eight switches are mapped to eight LEDs via VHDL programming. In addition to basic input-output mapping, the project focuses on the full design flow, which includes hardware implementation, synthesis, code entry, and timing analysis. To assure correct pin assignments and consistent signal timing during synthesis and implementation, constraints were applied using a User Constraints File (UCF). In order to confirm the design's stable operation within the FPGA's clock limits, setup and hold times were examined using post-synthesis timing reports. The approach also draws attention to typical issues with FPGA development, like signal synchronization, propagation latency, and resource usage. The final hardware testing validated the design flow's effectiveness in fulfilling timing and performance objectives in addition to functional correctness. Beginners are introduced to both functional and performance factors in hardware description and implementation through this work, providing a systematic example of FPGA-based digital design.